Lift-off techniques are finding increased interest and use in the fabrication of integrated circuits to achieve greater component density particularly in large scale integrated circuitry. Typical of the lift-off techniques are those described in U.S. Pat. Nos. 2,559,389, 3,849,136, 3,873,361 and 3,985,597.
One of the patents of particular interest is U.S. Pat. No. 3,985,597 which describes a process for forming an embedded interconnection system on a substrate by forming a first layer of an organic thermosetting polymerized resin layer (such as a polyimide) over the substrate; forming a second overlying layer of a material (such as a polysulfone) that is soluble in a solvent specific to it without appreciably affecting the material of the first layer (e.g. polyimide); forming a third thin barrier layer (e.g. SiO.sub.x, glass resin, etc.) resistive to ion etching in O.sub.2 on the second layer; depositing a resist layer; exposing the resist in a pattern of the desired metallurgy pattern; developing the resist to form a mask of the desired metallurgy pattern; reactive ion etching the resultant exposed areas of the first, second, and third layers; blanket depositing a conductive metal layer having a thickness approximately matching the thickness of the first layer (e.g. poyimide); and exposing the substrate to a solvent that is selective to the material of the second layer (e.g. polysulfone), which is removed together with the overlying portions of the barrier and metal layers.
In contrast to the above U.S. Pat. No. 3,985,597, which forms a conductive metal pattern within corresponding recessed openings or grooves of an insulating layer (e.g. polyimide), a particularly unique modification of the process is that of U.S. Pat. Nos. 4,035,276 and 4,090,006 in which an insulating layer (e.g. silicon dioxide, glass, etc) is deposited to embed a preformed conductor pattern coated by a release layer, where the release layer coated conductor pattern is formed by lift-off techniques. The release layer (e.g. copper, chrome, etc.) and the overlying insulator layer are subsequently removed by exposure to an etchant such as concentrated nitric acid.
Although an effective process is described therein, it is desireable to obtain a simpler process with further reduced deviation from planarity. For example, in the application of this process to aluminum based metallurgy (e.g. aluminum, aluminum/copper, and other alloys thereof), improved enhancement of registration is desireable for the next E-beam exposure processing, since it is difficult to distinguish adequately between aluminum based metallization and silicon dioxide or glass insulators which only have about a 1000A step between them. Also, it is desireable to protect the aluminum based metallization during etching of the release layer, and thus avoid pitting of the conductor pattern. These objectives become more significant in view of the substantial increases in densities of semiconductor devices, particularly with increasing levels of metallization. Such higher densities of the devices render them sensitive to fabrication tolerances. For example, four levels of metallization are becoming common in integrated circuit designs. Even with three levels of metallization, the integrated circuits become wire limited as the density of the device increases. A simpler and improved planar process is also necessary in order to maintain and insure good coverage of metal and insulators at all levels.